1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and more particularly, to a low leakage current SRAM.
2. Description of the Prior Art
As semiconductor technology improves, the diameter of wafers have been increased from 8 inches to 12 inches, and the line widths of transistors have been decreased from 0.18 μm to 0.13 μm, or to 0.1 μm. However, while semiconductor technology improves, sub-threshold leakages and gate leakages of the transistors become more and more severe and influence the behaviors of electric devices more obviously. Therefore, with the reduction of the line width, the leakage currents can make operations of SRAM diverge from specifications.
Please refer to FIG. 1, which is a schematic diagram of an SRAM 1 of the prior art. The SRAM 1 has a plurality of SRAM cells 10, which are arranged as a matrix, for storing data. Each of the SRAM cells 10 connects to a corresponding pair of bit lines 18 and a corresponding word line 20, and is controlled by the word lines 20 and the pair of bit lines 18. The SRAM 1 further has a plurality of sense amplifiers 24, which connect to the SRAM cells 10 via the bit lines 18. When data stored in the SRAM cells 10 are read, the sense amplifiers 24 amplify the data signal received from the bit lines 18.
Please refer to FIG. 2, which is a circuit diagram of the SRAM cell 10 shown in FIG. 1. The SRAM cell 10 is a 6T SRAM cell that is commonly and widely used in SRAM. The SRAM cell 10 has six transistors 12–16 and two power terminals SAP and SAN, where the power terminal SAP is connected to VDD the power terminal SAN is connected to VSS. The voltage level of VDD is usually positive, i.e. +1.5 volts, and voltage level of VSS is usually equal to zero volts. However, VSS may also be a negative voltage in specific applications. The two N-type metal-oxide-semiconductor (NMOS) transistors 12 of the SRAM cell 10 respectively connect to VSS, and two nodes A and B. The two nodes A and B are connected to VDD the two P-type metal-oxide-semiconductor (PMOS) transistors 14. Moreover, node A is connected to the gates of the right NMOS transistor 12 and the right PMOS transistor 14, and node B is connected to the gates of the left NMOS transistor 12 and the left PMOS transistor 14.
A flip-flop configuration is composed of the two NMOS transistors 12 and the two PMOS transistors 14 of the SRAM cell 10 so that data can be stored. When node A is at a logic low state, i.e. the voltage level of node A is approximately equal to VSS, the right PMOS transistor 14 is turned on and the right NMOS transistor 12 is turned off. When the right PMOS transistor 14 is turned on and the right NMOS transistor 12 is turned off, the voltage level of node B is at a logic high state, i.e. the voltage level of node B is pulled up to approximately VDD. Moreover, when node B is at the logic high state, the left PMOS transistor 14 is turned off and the left NMOS transistor 12 is turned on. When the left PMOS transistor 14 is turned off and the left NMOS transistor 12 is turned on, the voltage level of node A is pulled down. In this manner, the SRAM cell 10 remains in a latched state.
The two nodes A and B are respectively connected to the pair of bit lines 18 via the two NMOS transistors 16. The gates of the NMOS transistors 16 are connected to a corresponding world line 20. The bit lines 18 and the world line 20 are used to control read/write operations of the SRAM cell 10. During a read operation of the SRAM cell 10, the two NMOS transistors 16 are turned on by the world line 20 so that the voltage level of one of the two bit lines 18 is pulled up and the voltage level of another bit line 18 is pulled down. For instance, if node A is at the logic low state and the voltage level of the world line 20 is pulled up, the two PMOS transistors 16 are turned on. Meanwhile, the voltage of the left bit line BL is pulled down, and the voltage of the right bit line BLb is pulled up.
However, when node A is at the logic high state and the voltage level of the world line 20 is pulled down to turn off the two NMOS transistors 16, a sub-threshold leakage flows from node A through the left NMOS 12 to VSS. Please refer to FIG. 3, which shows the sub-threshold leakages 22 of the SRAM cell 10 when the SRAM cell 10 is not accessed. In this case, node A is at the logic high state and node B is at the logic low state. When the SRAM 10 is not accessed, i.e. in a standby state, the two NMOS transistors 16 are turned off, and the voltage levels of the two bit lines 18 connected with the drains of the NMOS transistors 16 are below VDD. Because the voltage level of node A is less than both VDD and the voltage level of the left bit line 18, there are two sub-threshold leakages 22 respectively flowing through the left PMOS transistor 14 and the left NMOS transistor 16 to node A. Moreover, because the voltage level of node B is greater than both VSS and the voltage level of the right bit line 18, there are two other sub-threshold leakages 22 respectively flowing from node B to the right bit line 18 and the power terminal SAN of the SRAM cell 10. There are such sub-threshold leakages 22 when the SRAM cell 10 is at the standby state, so if the number of SRAM cells 10 of the SRAM 1 is large, the total leakage of the SRAM 1 will be great and the operations of the SRAM 1 may become abnormal.